preliminary 512k x 8 static ram cy7c1049av33 gvt73512a8 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 june 15, 2000 33 features ? fast access times: 10, 12 ns fast oe access times: 5, 6 ns single +3.3v 0.3v power supply fully static?no clock or timing strobes necessary all inputs and outputs are ttl-compatible three0-state outputs center power and ground pins for greater noise immu- nity jedec standard for functionality and revolutionary pi- nout easy memory expansion with ce and oe options automatic ce power-down high-performance, low-power consumption, cmos double-poly, double-metal process functional description the cy7c1049av33 /gvt73512a8 is organized as a 524,288 x 8 sram using a four-transistor memory cell with a high-per- formance, silicon gate, low-power cmos process. cypress srams are fabricated using double-layer polysilicon, dou- ble-layer metal technology. this device offers center power and ground pins for improved performance and noise immunity. static design eliminates the need for external clocks or timing strobes. for increased sys- tem flexibility and eliminating bus contention problems, this de- vice offers chip enable (ce ) and output enable (oe ) with this organization. writing to these devices is accomplished when write enable (we ) and chip enable (ce ) inputs are both low. reading is accomplished when (ce ) and (oe ) go low with (we ) remain- ing high. the device offers a low-power standby mode when chip is not selected. this allows system designers to meet low standby power requirements. functional block diagram ce# address buffer row decoder column decoder memory array 1024 rows x 512 x 8 columns i/o control we# oe# dq 8 dq 1 power down a 18 a 0 v cc v ss selection guide cy7c1049av33 -10/ gvt73512a8-10 cy7c1049av33 -12/ gvt73512a8-12 maximum access time (ns) 10 12 maximum operating current (ma) 240 210 maximum cmos standby current (ma) com?l/ind?l 10 10 com?l l3.0 3.0
cy7c1049av33 gvt73512a8 preliminary 2 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) voltage on v cc supply relative to v ss ......... ? 0.5v to +4.6v v in ........................................................... ? 0.5v to v cc +0.5v storage temperature (plastic)........................ ? 55 c to +125 junction temperature ..................................................+125 power dissipation ......................................................... 1.2w short circuit output current ....................................... 50 ma note: 1. t a is the ? instant on ? case temperature. 1 2 3 4 5 6 7 8 9 10 11 14 23 24 28 27 26 25 29 32 31 30 to p v iew soj 12 13 33 36 35 34 16 15 21 22 v ss a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 we v cc a 18 a 15 a 12 a 14 dq 6 dq 5 a 9 a 0 dq 1 dq 2 dq 3 oe a 17 a 16 a 13 ce 18 17 19 20 v ss dq 8 dq 4 dq 7 v cc a 10 a 11 nc nc pin configuration truth table mode ce we oe dq power read l h l q active write l l x d active output disable l h h high-z active standby h x x high-z standby pin descriptions pin name type description a 0 ? a 18 input addresses inputs: these inputs determine which cell is addressed. we input write enable: this input determines if the cycle is a read or write cycle. we is low for a write cycle and high for a read cycle. ce input chip enable: this active low input is used to enable the device. when ce is low, the chip is selected. when ce is high, the chip is disabled and automatically goes into standby power mode. oe input output enable: this active low input enables the output drivers. dq 1 ? dq 8 input/output sram data i/o: data inputs and data outputs. v cc supply power supply: 3.3v 0.3v. v ss supply ground. operating range range ambient temperature [1] v cc commercial 0 c to +70 c 3.3v 0.3v industrial ? 40 c to +85 c
cy7c1049av33 gvt73512a8 preliminary 3 electrical characteristics over the operating range parameter description conditions min. max. unit v ih input high (logic 1) voltage [2, 3] 2.2 v cc +0.5 v v il input low (logic 0) voltage [2, 3] ? 0.5 0.8 v il i input leakage current 0v < v in < v cc ? 55 a il o output leakage current output(s) disabled, 0v < v out < v cc ? 55 a v oh output high voltage [2] i oh = ? 4.0 ma 2.4 v v ol output low voltage [2] i ol = 8.0 ma 0.4 v vcc supply voltage [2] 3.0 3.6 v parameter description conditions power typ. -10 -12 unit i cc power supply current: operating [4, 5] device selected; ce < v il ; v cc = max.; f=f max ; outputs open standard 90 240 210 ma low 240 210 i sb1 ttl standby [5] ce > v ih ; v cc = max.; f = f max standard 30 70 60 ma low 70 60 i sb2 cmos standby [5] ce1 > v cc ? 0.2; v cc = max.; all other inputs < v ss + 0.2 or > v cc ? 0.2; all inputs static; f= 0 standard 0.1 10 10 ma low 3.0 3.0 capacitance [6] parameter description test conditions max. unit c i input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3v 6pf c i/o input/output capacitance (dq) 8pf note: 2. all voltages referenced to v ss (gnd). 3. overshoot: v ih < +6.0v for t < t rc /2. undershoot: v il < ? 2.0v for t < t rc /2 4. i cc is given with no output current. i cc increases with greater output loading and faster cycle times. 5. typical values are measured at 3.3v, 25 c, and 20 ns cycle time. 6. this parameter is sampled. ac test loads and waveforms 90% 10% 3.3v 0v 90% 10% all input pulses (a) (b) vt = 1.5v 30 pf dq z 0 = 50 ? 50 ? dq 3.3v 317 ? 351 ? 5 pf rise time: 1 v/ns fall time: 1 v/ns
cy7c1049av33 gvt73512a8 preliminary 4 switching characteristics [5] over the operating range 7c1049av33-10/ gvt73512a8-10 7c1049av33-12/ gvt73512a8-12 parameter description min. max. min. max. unit read cycle t rc read cycle time 10 12 ns t aa address access time 10 12 ns t ace chip enable access time 10 12 ns t oh output hold from address change 3 3 ns t lzce chip enable to output in low-z [6, 7] 33ns t hzce chip disable to output in high-z [6, 7, 8] 56ns t aoe output enable access time 5 6 ns t lzoe output enable to output in low-z 0 0 ns t hzoe output enable to output in high-z [6, 8] 56ns t pu chip enable to power-up time [6] 00ns t pd chip disable to power-down time [6] 10 12 ns write cycle t wc write cycle time 10 12 ns t cw chip enable to end of write 8 8 ns t aw address valid to end of write, with oe high 8 8 ns t as address set-up time 0 0 ns t ah address hold from end of write 0 0 ns t wp2 write pulse width 10 10 ns t wp1 write pulse width, with oe high 8 8 ns t ds data set-up time 5 6 ns t dh data hold time 0 0 ns t lzwe write disable to output in low-z [6, 7] 34ns t hzwe write enable to output in high-z [6, 7, 8] 66ns data retention characteristics over the operating range (for l version only) parameter description conditions min. typ. max. unit v dr v cc for data retention 2.0 v i ccdr [9] data retention current ce > v cc ? 0.2v; all other inputs < v ss + 0.2 or > v cc ? 0.2; all inputs static; f = 0 v cc = 2v 0.2 1.6 ma v cc = 3v 0.3 2.4 ma t cdr [6] chip deselect to data retention time 0ns t r [6, 10] operation recovery time t rc ns notes: 7. at any given temperature and voltage condition, t hzce is less than t lzce and t hzwe is less than t lzwe . 8. output loading is specified with c l =5 pf as in ac test loads. transition is measured 500mv from steady state voltage. 9. capacitance derating applies to capacitance different from the load capacitance shown in ac test loads. 10. t rc = read cycle time.
cy7c1049av33 gvt73512a8 preliminary 5 low v cc data retention waveform switching waveforms read cycle no. 1 [11, 12] read cycle no. 2 [7, 11, 13, 14] notes: 11. we is high for read cycle. 12. device is continuously selected. chip enable and output enables are held in their active state. 13. address valid prior to or coincident with latest occurring chip enable. 14. chip enable and write enable can initiate and terminate a write cycle. v cc ce# data retention mode v dr 3.0v 3.0v v ih v il t rc t cdr previous data valid data valid t rc t aa t oha addr q valid data valid t rc t ace t lzce high z t hzoe t hzce oe ce q aoe t t lzoe
cy7c1049av33 gvt73512a8 preliminary 6 write cycle no. 1 (we controlled with oe active low) [9, 7, 14] write cycle no. 2 (we controlled with oe inactive high) [9, 14] switching waveforms (continued) addr t wc t ah t ds data valid ce# we# d q t dh t wp2 t as t aw t cw high z t hzwe t lzwe ble# bhe# t bw addr t wc t ah t ds data valid high z ce# we# d q t dh t wp1 t as t aw t cw ble# bhe# t bw
cy7c1049av33 gvt73512a8 preliminary 7 document #: 38 ? 00996-** write cycle no. 3 (ce controlled) [9, 14] switching waveforms (continued) addr t wc t ah t ds data valid ce# we# d q t dh t wp1 t aw t cw high z t as ordering information speed (ns) ordering code package name package type operating range 10 cy7c1049av33 -10vc v36 36-lead (400-mil) molded soj commercial gvt73512a8j-10c cy7c1049av33 l-10vc v36 36-lead (400-mil) molded soj gvt73512a8j-10lc 12 cy7c1049av33 -12vc v36 36-lead (400-mil) molded soj gvt73512a8j-12c cy7c1049av33 l-12vc v36 36-lead (400-mil) molded soj GVT73512A8J-12LC
cy7c1049av33 gvt73512a8 preliminary ? cypress semiconductor corporation, 2000. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package diagram 36-lead (400-mil) molded soj v36 51-85090
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